/* udis86 - libudis86/decode.c

 * 

 * Copyright (c) 2002-2009 Vivek Thampi

 * All rights reserved.

 * 

 * Redistribution and use in source and binary forms, with or without modification, 

 * are permitted provided that the following conditions are met:

 * 

 *     * Redistributions of source code must retain the above copyright notice, 

 *       this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright notice, 

 *       this list of conditions and the following disclaimer in the documentation 

 *       and/or other materials provided with the distribution.

 * 

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 

 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 

 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 

 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 

 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

#include "udint.h"

#include "types.h"

#include "decode.h"

#ifndef __UD_STANDALONE__

# include <string.h>

#endif /* __UD_STANDALONE__ */

/* The max number of prefixes to an instruction */

#define MAX_PREFIXES    15

/* rex prefix bits */

#define REX_W(r)        ( ( 0xF & ( r ) )  >> 3 )

#define REX_R(r)        ( ( 0x7 & ( r ) )  >> 2 )

#define REX_X(r)        ( ( 0x3 & ( r ) )  >> 1 )

#define REX_B(r)        ( ( 0x1 & ( r ) )  >> 0 )

#define REX_PFX_MASK(n) ( ( P_REXW(n) << 3 ) | \

                          ( P_REXR(n) << 2 ) | \

                          ( P_REXX(n) << 1 ) | \

                          ( P_REXB(n) << 0 ) )

/* scable-index-base bits */

#define SIB_S(b)        ( ( b ) >> 6 )

#define SIB_I(b)        ( ( ( b ) >> 3 ) & 7 )

#define SIB_B(b)        ( ( b ) & 7 )

/* modrm bits */

#define MODRM_REG(b)    ( ( ( b ) >> 3 ) & 7 )

#define MODRM_NNN(b)    ( ( ( b ) >> 3 ) & 7 )

#define MODRM_MOD(b)    ( ( ( b ) >> 6 ) & 3 )

#define MODRM_RM(b)     ( ( b ) & 7 )

static int decode_ext(struct ud *u, uint16_t ptr);

enum reg_class { /* register classes */

  REGCLASS_GPR,

  REGCLASS_MMX,

  REGCLASS_CR,

  REGCLASS_DB,

  REGCLASS_SEG,

  REGCLASS_XMM

};

 /* 

 * inp_start

 *    Should be called before each de-code operation.

 */

static void

inp_start(struct ud *u)

{

  u->inp_ctr = 0;

}

static uint8_t

inp_next(struct ud *u)

{

  if (u->inp_end == 0) {

    if (u->inp_buf != NULL) {

      if (u->inp_buf_index < u->inp_buf_size) {

        u->inp_ctr++;

        return (u->inp_curr = u->inp_buf[u->inp_buf_index++]);

      }

    } else {

      int c;

      if ((c = u->inp_hook(u)) != UD_EOI) {

        u->inp_curr = c;

        u->inp_sess[u->inp_ctr++] = u->inp_curr;

        return u->inp_curr;

      }

    }

  }

  u->inp_end = 1;

  UDERR(u, "byte expected, eoi received\n");

  return 0;

}

static uint8_t

inp_curr(struct ud *u)

{

  return u->inp_curr;

}

/*

 * inp_uint8

 * int_uint16

 * int_uint32

 * int_uint64

 *    Load little-endian values from input

 */

static uint8_t 

inp_uint8(struct ud* u)

{

  return inp_next(u);

}

static uint16_t 

inp_uint16(struct ud* u)

{

  uint16_t r, ret;

  ret = inp_next(u);

  r = inp_next(u);

  return ret | (r << 8);

}

static uint32_t 

inp_uint32(struct ud* u)

{

  uint32_t r, ret;

  ret = inp_next(u);

  r = inp_next(u);

  ret = ret | (r << 8);

  r = inp_next(u);

  ret = ret | (r << 16);

  r = inp_next(u);

  return ret | (r << 24);

}

static uint64_t 

inp_uint64(struct ud* u)

{

  uint64_t r, ret;

  ret = inp_next(u);

  r = inp_next(u);

  ret = ret | (r << 8);

  r = inp_next(u);

  ret = ret | (r << 16);

  r = inp_next(u);

  ret = ret | (r << 24);

  r = inp_next(u);

  ret = ret | (r << 32);

  r = inp_next(u);

  ret = ret | (r << 40);

  r = inp_next(u);

  ret = ret | (r << 48);

  r = inp_next(u);

  return ret | (r << 56);

}

static inline int

eff_opr_mode(int dis_mode, int rex_w, int pfx_opr)

{

  if (dis_mode == 64) {

    return rex_w ? 64 : (pfx_opr ? 16 : 32);

  } else if (dis_mode == 32) {

    return pfx_opr ? 16 : 32;

  } else {

    UD_ASSERT(dis_mode == 16);

    return pfx_opr ? 32 : 16;

  }

}

static inline int

eff_adr_mode(int dis_mode, int pfx_adr)

{

  if (dis_mode == 64) {

    return pfx_adr ? 32 : 64;

  } else if (dis_mode == 32) {

    return pfx_adr ? 16 : 32;

  } else {

    UD_ASSERT(dis_mode == 16);

    return pfx_adr ? 32 : 16;

  }

}

/* 

 * decode_prefixes

 *

 *  Extracts instruction prefixes.

 */

static int 

decode_prefixes(struct ud *u)

{

  int done = 0;

  uint8_t curr, last = 0;

  UD_RETURN_ON_ERROR(u);

  do {

    last = curr;

    curr = inp_next(u); 

    UD_RETURN_ON_ERROR(u);

    if (u->inp_ctr == MAX_INSN_LENGTH) {

      UD_RETURN_WITH_ERROR(u, "max instruction length");

    }

    switch (curr)  

    {

    case 0x2E: 

      u->pfx_seg = UD_R_CS; 

      break;

    case 0x36:     

      u->pfx_seg = UD_R_SS; 

      break;

    case 0x3E: 

      u->pfx_seg = UD_R_DS; 

      break;

    case 0x26: 

      u->pfx_seg = UD_R_ES; 

      break;

    case 0x64: 

      u->pfx_seg = UD_R_FS; 

      break;

    case 0x65: 

      u->pfx_seg = UD_R_GS; 

      break;

    case 0x67: /* adress-size override prefix */ 

      u->pfx_adr = 0x67;

      break;

    case 0xF0: 

      u->pfx_lock = 0xF0;

      break;

    case 0x66: 

      u->pfx_opr = 0x66;

      break;

    case 0xF2:

      u->pfx_str = 0xf2;

      break;

    case 0xF3:

      u->pfx_str = 0xf3;

      break;

    default:

      /* consume if rex */

      done = (u->dis_mode == 64 && (curr & 0xF0) == 0x40) ? 0 : 1;

      break;

    }

  } while (!done);

  /* rex prefixes in 64bit mode, must be the last prefix */

  if (u->dis_mode == 64 && (last & 0xF0) == 0x40) {

    u->pfx_rex = last;  

  }

  return 0;

}

static inline unsigned int modrm( struct ud * u )

{

    if ( !u->have_modrm ) {

        u->modrm = inp_next( u );

        u->have_modrm = 1;

    }

    return u->modrm;

}

static unsigned int

resolve_operand_size( const struct ud * u, unsigned int s )

{

    switch ( s ) 

    {

    case SZ_V:

        return ( u->opr_mode );

    case SZ_Z:  

        return ( u->opr_mode == 16 ) ? 16 : 32;

    case SZ_Y:

        return ( u->opr_mode == 16 ) ? 32 : u->opr_mode;

    case SZ_RDQ:

        return ( u->dis_mode == 64 ) ? 64 : 32;

    default:

        return s;

    }

}

static int resolve_mnemonic( struct ud* u )

{

  /* resolve 3dnow weirdness. */

  if ( u->mnemonic == UD_I3dnow ) {

    u->mnemonic = ud_itab[ u->le->table[ inp_curr( u )  ] ].mnemonic;

  }

  /* SWAPGS is only valid in 64bits mode */

  if ( u->mnemonic == UD_Iswapgs && u->dis_mode != 64 ) {

    UDERR(u, "swapgs invalid in 64bits mode\n");

    return -1;

  }

  if (u->mnemonic == UD_Ixchg) {

    if ((u->operand[0].type == UD_OP_REG && u->operand[0].base == UD_R_AX  &&

         u->operand[1].type == UD_OP_REG && u->operand[1].base == UD_R_AX) ||

        (u->operand[0].type == UD_OP_REG && u->operand[0].base == UD_R_EAX &&

         u->operand[1].type == UD_OP_REG && u->operand[1].base == UD_R_EAX)) {

      u->operand[0].type = UD_NONE;

      u->operand[1].type = UD_NONE;

      u->mnemonic = UD_Inop;

    }

  }

  if (u->mnemonic == UD_Inop && u->pfx_repe) {

    u->pfx_repe = 0;

    u->mnemonic = UD_Ipause;

  }

  return 0;

}

/* -----------------------------------------------------------------------------

 * decode_a()- Decodes operands of the type seg:offset

 * -----------------------------------------------------------------------------

 */

static void 

decode_a(struct ud* u, struct ud_operand *op)

{

  if (u->opr_mode == 16) {  

    /* seg16:off16 */

    op->type = UD_OP_PTR;

    op->size = 32;

    op->lval.ptr.off = inp_uint16(u);

    op->lval.ptr.seg = inp_uint16(u);

  } else {

    /* seg16:off32 */

    op->type = UD_OP_PTR;

    op->size = 48;

    op->lval.ptr.off = inp_uint32(u);

    op->lval.ptr.seg = inp_uint16(u);

  }

}

/* -----------------------------------------------------------------------------

 * decode_gpr() - Returns decoded General Purpose Register 

 * -----------------------------------------------------------------------------

 */

static enum ud_type 

decode_gpr(register struct ud* u, unsigned int s, unsigned char rm)

{

  switch (s) {

    case 64:

        return UD_R_RAX + rm;

    case 32:

        return UD_R_EAX + rm;

    case 16:

        return UD_R_AX  + rm;

    case  8:

        if (u->dis_mode == 64 && u->pfx_rex) {

            if (rm >= 4)

                return UD_R_SPL + (rm-4);

            return UD_R_AL + rm;

        } else return UD_R_AL + rm;

    case 0:

        /* invalid size in case of a decode error */

        UD_ASSERT(u->error);

        return UD_NONE;

    default:

        UD_ASSERT(!"invalid operand size");

        return UD_NONE;

  }

}

static void

decode_reg(struct ud *u, 

           struct ud_operand *opr,

           int type,

           int num,

           int size)

{

  int reg;

  size = resolve_operand_size(u, size);

  switch (type) {

    case REGCLASS_GPR : reg = decode_gpr(u, size, num); break;

    case REGCLASS_MMX : reg = UD_R_MM0  + (num & 7); break;

    case REGCLASS_XMM : reg = UD_R_XMM0 + num; break;

    case REGCLASS_CR : reg = UD_R_CR0  + num; break;

    case REGCLASS_DB : reg = UD_R_DR0  + num; break;

    case REGCLASS_SEG : {

      /*

       * Only 6 segment registers, anything else is an error.

       */

      if ((num & 7) > 5) {

        UDERR(u, "invalid segment register value\n");

        return;

      } else {

        reg = UD_R_ES + (num & 7);

      }

      break;

    }

    default:

      UD_ASSERT(!"invalid register type");

      return;

  }

  opr->type = UD_OP_REG;

  opr->base = reg;

  opr->size = size;

}

/*

 * decode_imm 

 *

 *    Decode Immediate values.

 */

static void 

decode_imm(struct ud* u, unsigned int size, struct ud_operand *op)

{

  op->size = resolve_operand_size(u, size);

  op->type = UD_OP_IMM;

  switch (op->size) {

  case  8: op->lval.sbyte = inp_uint8(u);   break;

  case 16: op->lval.uword = inp_uint16(u);  break;

  case 32: op->lval.udword = inp_uint32(u); break;

  case 64: op->lval.uqword = inp_uint64(u); break;

  default: return;

  }

}

/* 

 * decode_mem_disp

 *

 *    Decode mem address displacement.

 */

static void 

decode_mem_disp(struct ud* u, unsigned int size, struct ud_operand *op)

{

  switch (size) {

  case 8:

    op->offset = 8; 

    op->lval.ubyte  = inp_uint8(u);

    break;

  case 16:

    op->offset = 16; 

    op->lval.uword  = inp_uint16(u); 

    break;

  case 32:

    op->offset = 32; 

    op->lval.udword = inp_uint32(u); 

    break;

  case 64:

    op->offset = 64; 

    op->lval.uqword = inp_uint64(u); 

    break;

  default:

      return;

  }

}

/*

 * decode_modrm_reg

 *

 *    Decodes reg field of mod/rm byte

 * 

 */

static inline void

decode_modrm_reg(struct ud         *u, 

                 struct ud_operand *operand,

                 unsigned int       type,

                 unsigned int       size)

{

  uint8_t reg = (REX_R(u->pfx_rex) << 3) | MODRM_REG(modrm(u));

  decode_reg(u, operand, type, reg, size);

}

/*

 * decode_modrm_rm

 *

 *    Decodes rm field of mod/rm byte

 * 

 */

static void 

decode_modrm_rm(struct ud         *u, 

                struct ud_operand *op,

                unsigned char      type,    /* register type */

                unsigned int       size)    /* operand size */

{

  size_t offset = 0;

  unsigned char mod, rm;

  /* get mod, r/m and reg fields */

  mod = MODRM_MOD(modrm(u));

  rm  = (REX_B(u->pfx_rex) << 3) | MODRM_RM(modrm(u));

  /* 

   * If mod is 11b, then the modrm.rm specifies a register.

   *

   */

  if (mod == 3) {

    decode_reg(u, op, type, rm, size);

    return;

  }

  /* 

   * !11b => Memory Address

   */  

  op->type = UD_OP_MEM;

  op->size = resolve_operand_size(u, size);

  if (u->adr_mode == 64) {

    op->base = UD_R_RAX + rm;

    if (mod == 1) {

      offset = 8;

    } else if (mod == 2) {

      offset = 32;

    } else if (mod == 0 && (rm & 7) == 5) {           

      op->base = UD_R_RIP;

      offset = 32;

    } else {