"{ Encoding: utf8 }"

"

    Copyright (c) 2012-2016 Igor Stasenko

                            Martin McClure

                            Damien Pollet

                            Camillo Bruni

                            Guido Chari

                   2016-now Jan Vrany <jan.vrany [at] fit . cvut . cz>

    Permission is hereby granted, free of charge, to any person obtaining a copy

    of this software and associated documentation files (the 'Software'), to deal

    in the Software without restriction, including without limitation the rights

    to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

    copies of the Software, and to permit persons to whom the Software is

    furnished to do so, subject to the following conditions:

    The above copyright notice and this permission notice shall be included in all

    copies or substantial portions of the Software.

    THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

    AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

    SOFTWARE.

"

"{ Package: 'jv:dragonfly/asm' }"

"{ NameSpace: Smalltalk }"

AJInstruction subclass:#AJx86Instruction

	instanceVariableNames:'description'

	classVariableNames:''

	poolDictionaries:''

	category:'AsmJit-x86-Instructions'

!

!AJx86Instruction class methodsFor:'documentation'!

copyright

"

    Copyright (c) 2012-2016 Igor Stasenko

                            Martin McClure

                            Damien Pollet

                            Camillo Bruni

                            Guido Chari

                   2016-now Jan Vrany <jan.vrany [at] fit . cvut . cz>

    Permission is hereby granted, free of charge, to any person obtaining a copy

    of this software and associated documentation files (the 'Software'), to deal

    in the Software without restriction, including without limitation the rights

    to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

    copies of the Software, and to permit persons to whom the Software is

    furnished to do so, subject to the following conditions:

    The above copyright notice and this permission notice shall be included in all

    copies or substantial portions of the Software.

    THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

    AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

    SOFTWARE.

"

! !

!AJx86Instruction methodsFor:'accessing'!

description

    ^ description

!

description: anInstructionDescription

    description := anInstructionDescription

!

instructionDesciptions

    ^ AJx86InstructionDescription instructions

! !

!AJx86Instruction methodsFor:'code generation'!

emitByte: byte

    self assert: byte isByte.

    machineCode nextPut: byte 

!

emitCode: asm

    "do not generate machine code if it is already there"

    machineCode ifNotNil: [ ^ self ].

    "make sure all operands are converted"

    operands ifNotNil: [ operands := operands collect: #asAJOperand ].

    machineCode := WriteStream on: (ByteArray new: 16).		

    description emitUsing: self operands: operands.

    machineCode := machineCode contents.

!

emitDWord: dword

 	"Emit dword (4 bytes) in little-endian order (since our target it x86 anyways)"

	self 

		emitByte: (dword bitAnd: 255);

		emitByte: (dword>>8 bitAnd: 255);

		emitByte: (dword>>16 bitAnd: 255);

		emitByte: (dword>>24 bitAnd: 255)

!

emitImmediate: imm size: size

    ^ imm emitUsing: self size: size

!

emitMod: mod reg: reg rm: rm

    "Emit MODR/M byte.

    mmrrrxxx

    mm = mod

    rrr = REG (r8/r16/r32/mm/xmm

    xxx = r/m

    "

    ^ self emitByte: (mod & 3) << 3 + (reg & 7) << 3 + (rm & 7)

!

emitOpCode: opCode

    | byte |

    "instruction prefix"

    (byte := (opCode bitAnd: 16rFF000000)) = 0 ifFalse: [

        self emitByte: byte >> 24 ].

    (byte := (opCode bitAnd: 16r00FF0000)) = 0 ifFalse: [

        self emitByte: byte >> 16 ].

    (byte := (opCode bitAnd: 16r0000FF00)) = 0 ifFalse: [

        self emitByte: byte >> 8 ].

    self emitByte: (opCode bitAnd: 16rFF).

!

emitQWord: dword

 	"Emit a qword (8 bytes) in little-endian order (since our target it x86 anyways)"

	self 

		emitByte: (dword bitAnd: 255);

		emitByte: (dword>>8 bitAnd: 255);

		emitByte: (dword>>16 bitAnd: 255);

		emitByte: (dword>>24 bitAnd: 255);

		emitByte: (dword>>32 bitAnd: 255);

		emitByte: (dword>>40 bitAnd: 255);

		emitByte: (dword>>48 bitAnd: 255);

		emitByte: (dword>>56 bitAnd: 255)

!

emitRexForInteger: anInt op2: op2

    self emitRexPrefixW: op2 is64 R: false X: false  B:  op2 isUpperBank.

!

emitRexForOp1: op1 op2: op2

    "op1 is the general-purpose register argument (or a register number).

    op2 is the reg/mem argument.

    In 64-bit mode, the instruction's default operation size is 32 bits. 

    Use of the REX.W prefix promotes operation to 64 bits. 

    Use of the REX.R prefix permits access to additional registers (R8-R15) for the op1 (reg) register. 

    Use of the REX.B prefix permits access to additional registers (R8-R15) for the op2 (r/m) register, or the base register of op2 if register indirect. 

    Use of the REX.X prefix permits access to additional registers (R8-R15) for the index register of op2, if indexed.

    See the summary chart at the beginning of this section for encoding data and limits."

    | requires64Bit |

    "no-op in 32 bit mode"

    self is32BitMode

        ifTrue: [ ^ self ].

    op1 isInteger

        ifTrue: [ ^ self emitRexForInteger: op1 op2: op2 ].

    requires64Bit := op1 is64 or: [ op2 isReg and: [ op2 is64 ] ].

    self

        emitRexPrefixW: requires64Bit

        R: op1 isUpperBank

        X: op2 hasUpperBankIndex

        B: op2 isUpperBank

!

emitRexForSingleOperand: op

    "In 64-bit mode, the instruction’s default operation size is 32 bits. 

    Use of the REX.W prefix promotes operation to 64 bits. 

    Use of the REX.B prefix permits access to additional registers (R8-R15). 

    See the summary chart at the beginning of this section for encoding data and limits."

    self emitRexPrefixW: op is64 R: false X: false B: op isUpperBank .

!

emitRexPrefixW: w R: r X: x B: b

    "

    field  bit   def

    -      7-4   2r0100 REX prefix identifier

    W      3     0 = Operand size determined by CS.D

                 1 = 64 Bit Operand Size

    R      2     Extension of the ModR/M reg field

    X      1     Extension of the SIB index field

    B      0     Extension of the ModR/M r/m field. SIB base field, or Opcode reg field

    "

    self requiresRex

        ifTrue: [ 

            self is32BitMode

                ifTrue: [ self error: 'Attempt to use a 64-bit-specific instruction or operand in 32-bit mode' ]

                ifFalse: [ self emitByte: 2r0100 << 4 | (w asBit << 3) | (r asBit << 2) | (x asBit << 1) | b asBit ] ]

!

emitRexR: w opReg: opReg regCode: regCode

    "no-op in 32 bit mode"

!

emitRexRM: opRequires64Bit regCode: regCode rm: rm

    self emitRexPrefixW: opRequires64Bit R: (regCode > 7) X: false B: rm isUpperBank

!

emitScale: shift index: indexCode base: baseCode

    self emitByte: ((shift << 3) + (indexCode bitAnd: 7) << 3) + (baseCode bitAnd: 7)

!

emitSegmentPrefix: aMem

    (aMem isMem and: [ aMem hasSegmentPrefix ]) ifTrue: [

        self emitByte: aMem segmentPrefixCode.

    ]

!

emitX86Inl: opCode reg: reg

    "Emit instruction where register is inlined to opcode."

    ^ self emitX86Inl: opCode reg: reg withRex: true

!

emitX86Inl: opCode reg: reg withRex: useREX

    "Emit instruction where register is inlined to opcode."

    | byte |

    "16 bit prefix"

    reg size == 2 

        ifTrue: [ self emitByte: 16r66 ].

    "instruction prefix"

    (byte := (opCode bitAnd: 16rFF000000)) = 0 ifFalse: [

        self emitByte: byte >> 24 ].

    useREX ifTrue: [ self emitRexForSingleOperand: reg ].

    (byte := (opCode bitAnd: 16r00FF0000)) = 0 ifFalse: [

        self emitByte: byte >> 16 ].

    (byte := (opCode bitAnd: 16r0000FF00)) = 0 ifFalse: [

        self emitByte: byte >> 8 ].

    self emitByte: (opCode bitAnd: 16rFF) + (reg code bitAnd: 7).

!

emitX86RM: opCode size: aSize regOrCode: regOrCode rm: regOrMem 

"Emit instruction with reg/memory operand."

    ^ self emitX86RM: opCode size: aSize regOrCode: regOrCode rm: regOrMem immSize: 0

!

emitX86RM: opCode size: aSize regOrCode: regOrCode rm: regOrMem immSize: immSize

    "Emit instruction with reg/memory operand."

    | byte code |

    code := regOrCode isInteger ifTrue: [ regOrCode ] ifFalse: [ regOrCode code ].

    "16 bit prefix"

    aSize == 2 ifTrue: [ self emitByte: 16r66 ].

    "segment prefix"

    self emitSegmentPrefix: regOrMem.

    "instruction prefix"

    (byte := (opCode bitAnd: 16rFF000000)) = 0 ifFalse: [

        self emitByte: byte >> 24 ].

    self emitRexForOp1: regOrCode op2: regOrMem.

    (byte := (opCode bitAnd: 16r00FF0000)) = 0 ifFalse: [

        self emitByte: byte >> 16 ].

    (byte := (opCode bitAnd: 16r0000FF00)) = 0 ifFalse: [

        self emitByte: byte >> 8 ].

    self emitByte: (opCode bitAnd: 16rFF).

    "ModR/M"

    ^ regOrMem emitModRM: self code: code immSize: immSize

!

setLabelPosition: label

    "set label position for immediate operand(s), if any"

    label position: self position + machineCode size.  

! !

!AJx86Instruction methodsFor:'code generation - prefixes'!

emitOperandSizeOverridePrefix: anOperand

    "If creating 64bit code, this must be called last of the prefix-generators, as the 64-bit prefixes are required to precede the opcode"

    "Switch to 16-bit operand mode for the next opcode if necessary"

    anOperand is16 ifTrue: [ self emitByte: 16r66].

    self emitRexRM: anOperand is64 regCode: 0 rm: anOperand

! !

!AJx86Instruction methodsFor:'consistency'!

checkOperandsForConflict

    "Signal an error if the given operands cannot be used together. Must be sent after operands are set."

    | prohibited required |

    required := self requiresRex.

    prohibited := false.

    operands

        do: [ :op | 

            (op isInteger not and: [ op prohibitsRex ])

                ifTrue: [ prohibited := true ] ].

    prohibited & required

        ifTrue: [ self error: 'Mix of operands that require and prohibit a REX prefix' ]

! !

!AJx86Instruction methodsFor:'emitting code'!

emitWord: aWord 

    "little-endian"

    self 

        emitByte: (aWord bitAnd: 255);

        emitByte: ((aWord >> 8) bitAnd: 255)

! !

!AJx86Instruction methodsFor:'testing'!

is32BitMode

    ^ true

!

is64BitMode

    ^ false

!

isGPNRegister: reg

    "answer true if given register is native general purpose register,

    matching the target native size i.e. 32 bits for x86 or 64 bits for x64"

    ^ reg isGeneralPurpose and: [ reg size = 4 ]

!

requiresRex

    ^false

! !

!AJx86Instruction methodsFor:'visitor'!

accept: anObject

    "generic instruction"

    ^ anObject visitInstruction: self

! !